boardwise

boardwise

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An agent harness for hardware engineers.

Current development version: 0.6.1 (prerelease). Published packages are in

[Releases](https://github.com/xianyuyijinban/boardwise/releases).

It lets an AI assistant (Claude Code, DeepSeek, Kimi Code — any of them)

actually read your schematic — components, nets, pins, not screenshots —

and do real work on it: review the board, mark the problems, edit with

your sign-off, export the fab files. EasyEDA Pro is the platform we know

inside-out today; KiCad is next, and the architecture has been

multi-platform from day one.

What it does

Review. With the editor open, one command:

boardwise checkup

You get a report: ERC/DRC, 23 design rules, which parts

still lack datasheets, and every finding pointing at a concrete

component, pin and net — with markers drawn on the canvas where the

problems are. On real boards it has caught things the designer had

missed — a current-sense circuit with no bias, that kind of problem.

You don't find those by matching rules against a netlist; you have to

check whether the architecture makes sense together. When a rail's

voltage lives only in your head, intent audit lists those nets and

asks once; the answer lands in a design-intent contract

(intent set-rail) and is never asked again. The PCB review stages

already landed have flagged real layout defects on real boards — a

motor driver's exposed pad whose copper pour was left as a thermal

island on a four-layer FOC driver, that class of problem.

Edit. Find a problem, get a change preview; nothing moves until you

approve; afterwards it reads back and re-reviews to confirm the problem

is actually gone. Edit kinds today: change a component value, add a

missing part, repair a single pin connection, insert an RC/divider

subcircuit, move a functional block.

Export. One export-fab writes the whole fab bundle — Gerber,

pick-and-place and BOM together. (There is no netlist export command;

the netlist is read internally for review, not written out as a file.)

Draw. You state the circuit intent — a divider, an RC low-pass, an

LDO; parts, values, which pin joins which net — and the drawing

compiler turns it into a sheet a human can read: where parts sit, how

wires run, where text goes so it doesn't sit on a wire. Wrong

connectivity, not enough room, a conflict with your locked placement —

it refuses rather than hand you a bad drawing. It compiles offline, and

it can also land into the open editor itself — placement, pin readback

before any wire, save, and a render of the result. Several modules

compose onto one page: what is already on the page becomes keep-outs,

your locked placements are honoured, every rail gets a flag, and one

draw discard takes a landed page back off.

Newer pieces worth knowing:

• Offline geometry render — checkup --file draws each board to

canvas-.svg (two views, findings highlighted); it is drawn from the

archived geometry, not a screenshot.

• parts accept-unknown — an engineer puts on record that a part's unknowns

are acceptable, so the datasheet gate stops owing it; it is not a pass, and

the conclusion still counts the accepted parts.

• KiCad bare net ids — a (net 3) with no name is read (as net#3) instead

of the whole board being refused for carrying no net names.

• V4 and cross-board evidence — archived V4 projects can review multiple PCBs

board by board, with duplicate-board and divergent-library refusal. An explicit

review --interconnect (also on checkup --file)